On-chip resistors and capacitors are commonly used in modern integrated circuits for a variety of purposes, including filtering signals in frequency. Resistor-capacitor (RC) circuits may be used to implement, e.g., low-pass filters, high-pass filters, or bandpass filters. Due to variations in process, voltage, and/or temperature, real (non-ideal) resistors and capacitors often exhibit considerable variation in resistance and capacitance, respectively. Such variation negatively impacts the precision and/or accuracy desired in filter characteristics, e.g., filter bandwidth.
Calibration techniques are commonly employed to compensate for such fluctuations in resistance and capacitance. A common technique is to adjust the capacitance of a variable capacitor for this purpose. Logic may be used to solve for the RC time constant commonly denoted by τ, which is the product of resistance R and capacitance C. Then, because RC filter characteristics such as filter bandwidth are related to τ (e.g., the cutoff frequency of a lowpass RC filter is given by fc=1/(2πRC) Hz), such a variable capacitor may be adjusted to achieve desired filter characteristics.
FIG. 1 is a block diagram of a conventional RC calibration circuit 100 utilizing the aforementioned calibration technique. Such a configuration is well-described in the literature, e.g., in U.S. Pat. No. 6,262,603, “RC Calibration Circuit with Reduced Power Consumption and Increased Accuracy” by Mohan et al. and in U.S. Pat. Pub. No. 2009/0108858, “Methods and Systems for Calibrating RC Circuits,” by Kao et al. Therefore, only the most salient features of the calibration circuit 100 are summarized hereinbelow.
Circuit 100 includes a resistor 110 and a variable capacitor 112 connected in parallel between a node N and ground. A current source 114 provides a current IN into node N. A voltage VN is defined across resistor 110 and capacitor 112. A switch 118 connects node N and ground when in a closed position. An analog comparator 122 provides at its output a comparison signal CMP at a first logic state when its input voltage VN is less than its input voltage VRef and at a second logic state when VN is greater than VRef. A digital counter 120 receiving a clock signal CLK and a switch pulse SW provides a count CT based on comparison signal CMP as described further below. A digital logic block 116 provides switch pulse SW to control switch 118 and digital counter 120. Digital logic 116 further provides a digital control word DCW to control variable capacitor 112
Prior to operation of the calibration circuit 100, switch 118 is closed, and VN is at ground voltage. When operation begins at time t0, digital logic 116 outputs switch pulse SW. In response to the rising edge of pulse SW, switch 118 opens and counter 120 begins counting rising edges of clock signal CLK. Voltage VN then rises according to the following equation:VN=Vmax(1−et/τ),  (1)where Vmax represents the maximum voltage across capacitor 112, t represents elapsed time, and τ represents the RC time constant. When VN exceeds VRef (at a time denoted by t1), comparator 122 changes the logic state of signal CMP, causing counter 120 to stop counting. Digital logic 116 captures the value of count CT at this time. Then, the next falling edge of pulse SW closes switch 118, causing VN to discharge back to ground, and resets counter 120 in preparation for another round of calibration.
Digital logic 116 uses the captured count CT of the number of clock pulses to solve equation (1) for τ, making use of the fact that VN=VRef at time t1 (within one significant bit of count CT). The calculated (measured) value of τ is compared with the desired RC constant, and digital logic sends a control word DCW to increase (if the calculated τ is less than the desired RC constant) or decrease (if the calculated τ is greater than the desired RC constant) the capacitance of variable capacitor 112. Thus, the calibration circuit 100 is calibrated to maintain a desired time constant RC.
FIG. 2 is a block diagram of a conventional technique for calibrating an RC circuit 200 using a variable bandwidth code that may be set to a desired bandwidth setting at each calibration. Much like calibration circuit 100, calibration circuit 200 employs a feedback configuration whereby a code, viz., capacitive code (CC) 250, is iteratively provided to adjust variable capacitance until a terminating condition corresponding to successful calibration is met. Unlike calibration circuit 100, however, calibration circuit 200 provides a bandwidth code (BWC) 241 that indicates a reference value for calibration. The prior art calibration circuit 200 has been described at U.S. Pat. Pub. No. 2009/0108858, “Methods and Systems for Calibrating RC Circuits,” by Kao et al. and in Kuo et al., “A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 3, p. 745-46 (March 2009); therefore, only the most salient features of the circuit are summarized hereinbelow.
Calibration circuit 200 comprises an integrator 260 employing resistors and capacitors configured to provide a voltage Von to a comparator 226, which may be a digital or analog comparator. The integrator 260 includes an operational amplifier (op-amp) 214, variable capacitors 220, 222, and switches 219-1, 219-2, 219-3. Inputs to operational amplifier 214 are coupled by way of resistors 250-1 and 250-2 to nodes at voltages V1 and V2, respectively, which are in turn coupled to other resistors and an amplifier as shown in FIG. 2. When switches 219-1 and 219-2 are closed, voltages Vop and Von at output terminals 216, 218, respectively of op-amp 214 are at a common mode (CM) point of the op-amp. When the switches are opened, as described in further detail below, capacitors 220 and 222 discharge, causing Vop to be charged to a maximum positive voltage output of op-amp 214 and causing Von to be charged to a maximum negative voltage output. Comparator 226 compares Von with a reference voltage VRef. Based on a counter 232 that counts clock pulses and based on bandwidth code 241, capacitive code 250 is updated, and the iterative feedback loop continues until a terminating condition is met as described below.
Specifically, a source clock 228 provides clock pulses CLKIN to a frequency divider 230, which generates clock pulses CLKA by reducing the frequency of CLKIN by 2M, where M is an integer indicating the number of comparisons performed by comparator 226 in one period of CLKA. N-bit counter 232 counts the number of pulses of CLKA, where N is the number of bits used to calculate the capacitance of capacitors 220, 222. Frequency divider 234 generates clock pulses CLKB by reducing the frequency of CLKA by 2N+1. CLKB drives switches 219-1, 219-2, 219-3 and is also provided to comparator 226. At an initial time t0, CLKA, CLKB, and CLKIN are high, and switches 219-1, 219-2, 219-3 are closed, and Von and Vop are at a common mode point Vcm. At a falling edge of CLKB occurring at a time t1, switches 219-1, 219-2, 219-3 are pulsed open, capacitors 220, 222 discharge, and Von starts decreasing. Counter 232 starts counting pulses of CLKA until Von falls below or equal Vref at a time t2 as determined by comparator 226, at which time comparator 226 generates a signal 236 (denoted STOP in FIG. 2) causing counter 232 to stop counting and capture the counter value. Then, at a subsequent time t3 corresponding to the next rising edge of CLKB, switches 219-1, 219-2, 219-3 are closed and the cycle repeats. The capacitances for capacitors 220, 222 are updated based on the counter value as follows.
Subtractor 238 subtracts the count corresponding to the captured counter value from an N-bit bandwidth code 241 provided by a bandwidth code (BWC) controller 240. The manner in which the bandwidth code is provided is described in detail further below. If the difference calculated by subtractor 238 is zero as shown by calculation 242, a terminating condition is reached, and power to the calibration circuit 200 is cut off via cutoff circuit 244, because a difference of zero corresponds to an RC time constant operating at a predetermined time constant value as determined by the bandwidth code. If the difference is nonzero, the difference is added to a present capacitance code 248, and capacitance code generator 224 consequently provides a new capacitance code 250 to update the capacitances of capacitors 220, 222.
The bandwidth code that enables calibration at different values is determined as follows. The difference in time between t1 and t2 (denoted Δt), i.e., between when capacitors 220, 222 start to discharge and when Von drops below (or equals) Vref, may be expressed as follows:
                                          Δ            ⁢                                                  ⁢            T                    =                                    RC              ⁢                                                Δ                  ⁢                                                                          ⁢                                      V                    out                                                                    Δ                  ⁢                                                                          ⁢                                      V                    in                                                                        -                                          1                                  f                  in                                            ⁢              BWC                                      ,                            (        2        )            where ΔVin=V1−V2, ΔVout=2(Vcm−Vref), and fin is an input clock frequency. This relationship simply relates decay of Von to the reference level Vref. Then, because BWC=(ΔT)(fin), the bandwidth code is computed based on the captured pulse count of counter 232 and the frequency of CLKIN. Thus, to calibrate an RC circuit at a desired channel bandwidth as in the prior art approach of FIG. 2, a simulation may first be performed to determine the length of time ΔT, and the needed bandwidth code is obtained. This approach offers greater flexibility than the approach of FIG. 1
Another approach for RC calibration is disclosed at U.S. Pat. Pub. No. 2007/0207760, “Method and System for Filter Calibration Using Fractional-N Frequency Synthesized Signals” by Kavadias et al. Kavadias is directed to filter calibration using frequency synthesized signals. Aspects of the method disclosed in Kavadias include generating a LO signal by a phase locked loop (PLL) circuit within a chip. A reference signal is generated based on the generated LO signal and a synthesizer control signal. A frequency response for a filter circuit integrated within the chip is calibrated by adjusting parameters associated with the filter circuit based on the generated LO signal. Aspects of the system include a single-chip multi-band RF receiver that enables generation of a LO signal by a PLL circuit within the single-chip, and enables calibration of a frequency response for a filter circuit integrated within the chip. A reference signal is generated based on the generated LO signal and a synthesizer control signal. The frequency response is calibrated by adjusting the filter based on the generated reference signal.
RC calibration techniques that provide flexibility in calibrating to different RC time constants while offering greater accuracy than existing techniques are desired.